1. Field of the Invention
This invention relates to semiconductor circuits and structures. More specifically, this invention relates to a non-aligned MOSFET structure and process using resistors as the diffusions and capacitors as the gate for electrostatic discharge (ESD) protection.
2. Description of Related Art
Protection against ESD is a familiar problem in the design of semiconductor devices. It is common to use an NMOS FET device in bipolar mode (parasitic npn) with N+ type diffusions for the source and drain, and a channel formed in a P-well in a P-type substrate, as protection against ESD. In an NMOS FET, the source of the FET forms the emitter of the bipolar, the FET channel region between drain to source forms the base, and the drain forms the collector. When electron and holes are created by avalanche multiplication at the drain, the holes forward-bias the base-emitter junction and the parasitic bipolar turns on once the local substrate bios meets or exceeds approximately 0.7 volts (vbe). During normal operations, the NPN beneath the FET is turned off. During an ESD event, the NPN turns on at a trigger voltage and clamps the ESD voltage at the protected node (sustaining/holding voltage).
In today's advanced CMOS technologies, the NFET device used in parasitic bipolar npn mode during an ESD event is of limited use due to its relatively low second trigger current (It2), also known as thermal runaway current. The parasitic npn emitter consists of only a small section of the N-extension/source-drain sidewall due to the high vertical field, thus causing the bipolar action to occur mainly along the silicon/SiO2 interface. Since the effective emitter area of the bipolar during avalanche conditions is formed in a shallow region, the current density becomes very large during an avalanche/ESD event and causes a significant temperature increase in the region.
The problem with the typical NFET device used for ESD protection thus becomes twofold. First, the high vertical field causes the emitter/base/collector region of the bipolar to occur at the Si/SiO2 surface where the shallow extension region exists. This results in a high current density through this region during an ESD event. Second, the lighter doping in the extension region, combined with the high current density during an ESD event, causes a significant increase in the temperature of the silicon where the bipolar action is occurring, compared to the temperature in that region if the extension is not present. The NFET becomes a more efficient ESD device when the doping level and depth of the emitter/collector (extension region) is increased. This reduces the temperature in the silicon and increases the emitter efficiency in the extension region.
One way to increase the doping level in the emitter/collector is to eliminate the extension so that the emitter/collector is formed on the junction side wall instead of the extension side wall. A second way to reduce the impact of the extension is to form a deeper implant in the extension region.
Prior publications have disclosed using additional implants that are implanted at a higher dose/energy than the extension implant. Adding additional dopant into the extension region at a higher energy than the extension implant, makes the extension deeper and reduces the temperature in the silicon during an ESD event. The drawback to this prior art is that the process requires an additional mask.
The proposed invention increases the doping concentration and depth of the emitter/collector creating a more efficient bipolar. The device therefore operates at a lower temperature during an ESD event due to the reduced current density through the higher doped, deeper junctions which form the emitter/collector regions.
Bearing in mind the problems and deficiencies of the prior art, it is therefore an object of the present invention to provide a method and structure to decrease the current density and joule heating in an NFET ESD protection device during an ESD event.
It is another object of the present invention to provide a method and structure of reducing the current density through the shallow emitter area during an ESD event.
A further object of the invention is to provide a method and structure to lower the operating temperature of the emitter region during an ESD event.
It is yet another object of the present invention to provide a method and structure to form the emitter/collector on the junction side wall instead of the extension side wall.
It is yet still a further object of the present invention to provide a method and structure to implant a deeper implant into the extension region.
Another object of the present invention is to provide a method and structure to increase the doping level in the emitter/collector and eliminate the extension region.
Finally, yet another object of the present invention is to provide a method and structure to eliminate the need for additional masks in forming an NFET ESD protection device.
Still other objects and advantages of the invention will in part be obvious and will in part be apparent from the specification.